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Configuration of VLSI Arrays in the Presence of Defects
Circuit area fault tolerance percolation theory probabilistic analysis queuing processes systolic arrays
2015/8/14
The penalties for configuring VLSI arrays for yield enhancement are assessed. Each dement of the fabricated array is assumed to be defective with independent probability p. A fixed fractmn R of the el...
Modeling of the I–V Characteristics for LDD-nMOSFETs in Relation with Defects Induced by Hot-Carrier Injection
I–V characteristics MOS LDD Modeling Defects
2010/12/7
The hot-carrier injection is observed increasingly to degrade the I–V characteristics with the scaling of MOS transistors. For the lightly doped drain MOS transistor the injection of the hot-carriers,...